`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/24 16:43:53
// Design Name: 
// Module Name: alu
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module alu(
    clk,nop,data_1,data_2,op_alu,data_exe,zero,fw_1,fw_2,data_fw_1,data_fw_2
    );

    input clk,nop;
    input [31:0] data_1,data_2;
    input [2:0] op_alu;
    input [1:0] fw_1,fw_2;
    input [31:0] data_fw_1,data_fw_2;
    output reg zero;
    output reg [31:0] data_exe;
    
    reg [31:0] data;
    reg [31:0] data1,data2;

    parameter add=3'b0,sub=3'b1;

    always @(*) begin
        data1 = data_1;
        case (fw_1)
            2'b00 : data1 = data_fw_1;
            2'b01 : data1 = data_fw_2;
            2'b10 : data1 = data_1;
        endcase
    end

    always @(*) begin
        data2 = data_2;
        case (fw_2)
            2'b00 : data2 = data_fw_1;
            2'b01 : data2 = data_fw_2;
            2'b10 : data2 = data_2;
        endcase
    end

    always @(*) begin
        case (op_alu)
            add : data = data1 + data2;
            sub : data = data1 - data2;
            default : data = 32'bx;
        endcase
    end

    always @(posedge clk) begin
        if(nop) begin
            data_exe <= 32'bx;
        end
        else begin
            data_exe <= data;
        end
    end

    always @(posedge clk) begin
        if(nop) begin
            zero = 1;
        end
        else begin
            if(~data)
                zero = 0;
            else
                zero = 1;
        end
    end
endmodule
